The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organizations which include the Semiconductor Industry Associations of the US, Europe, Japan, Korea and Taiwan. The documents represent best opinion on the directions of research into the following areas of technology, including time-lines up to about 15 years into the future: System Drivers/Design, Test & Test Equipment, Front End Processes, Photolithography, IC Interconnects, Factory Integration, Assembly & Packaging, Environment, Safety & Health, Yield Enhancement, Metrology, Modeling & Simulation, Emerging Research Devices, and Emerging Research Materials.
In order to keep pace with the ITRS roadmap a strong focus on packaging is visible in the prior art, and in particular in the surface-mount technology (SMT). Within this field Quad Flat Packages (QFP) have been very popular for a long time. A QFP is an integrated circuit package with leads extending from each of the four sides. It has been primarily used for surface mounting (SMD). In the prior art versions have been reported in the range from 32 to over 200 pins with a pitch ranging from 0.4 to 1.0 mm. Special cases include Low-profile (LQFP) and Thin-QFP (TQFP). The QFP package type became common in Europe and US during the early nineties, but QFP components have been used in Japanese consumer electronics since the seventies, most often mixed with hole-mounted, and sometimes socketed, components on the same printed circuit board.
Quad-Flat-No-leads (QFN) or Microleadframe (MLF) packages physically and electrically connect integrated circuits to printed circuit boards. QFN is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. The QFN package is similar to the Quad Flat Package, but in QFN packages the terminals/leads are mainly at the package bottom side and do not or only slightly extend out from the package sides. This is a near chip scale package (CSP) plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. In most cases the package includes an exposed thermal pad to improve heat transfer out of the IC (into the PCB). Heat transfer can be further facilitated by metal vias in the thermal pad.
A problem of the known packages in surface-mount technology is that the bondpad pitch is still relatively large, which does not comply with the ITRS roadmap for the future.